This invention relates to a timing protection system for various control timings in a data processor, and more specifically to the realization of the timing function by the use of a dummy cycle executed by an instruction, particularly a micro-instruction.
In the case of processing machine instructions for external devices such as input/output units using microprograms, a first micro-instruction is executed for sending some data to the external devices and then a second micro-instruction is executed to process the response signal sent from such external devices.
The timing protection required for timing control of such external devices has been carried out using a timer or a complicated control circuit which confirms operation by exchanging response signals with the external devices, namely by an interlock system. In other words, such timing protection has required specially designed circuits or a complicated control system.